The present invention relates in general to communication systems, and is particularly directed to a digital data demodulator architecture, that employs a cordic rotator-based, digital phase locked loop for carrier frequency acquisition and tracking.
The radio frequency (RF) and intermediate frequency (IF) stages of conventional radio subsystems (including those which employ digital signal processing components), such as but not limited to modulator and demodulator stages, typically employ both fixed frequency and voltage controlled crystal oscillators as part of their frequency conversion stages (mixers) and phase locked loop circuits. A conventional phase locked loop for a demodulation stage of a conventional xe2x80x9cdigitalxe2x80x9d radio for demodulating a spread spectrum-modulated QPSK signal, as a non-limiting example, is diagrammatically illustrated in FIG. 1 as having an input port 10, to which an incoming signal to be demodulated is applied. Input port 10 is coupled to respective in-phase (I) and quadrature phase (Q) channel mixers 11 and 13, which multiply the incoming signal by relative phase quadrature reference frequency signals generated by a voltage controlled local oscillator (VCO) 15 and an associated 90xc2x0 phase shifter 17, so as to produce down-converted (baseband) I and Q channel signals.
The down-converted (baseband) I and Q channel signals output by mixers 11, 13 are digitized by an analog-to-digital converter 21 and then despread by a correlator 23. The respective despread baseband Ixe2x80x2 and Qxe2x80x2 channels output by the correlator 23 are coupled over respective multibit links 31 and 32 to digitally implemented phase error detection logic circuitry 33, which outputs a digital vector (code) representative of the (carrier frequency offset associated) phase error in the downconverted signals. This phase error code is coupled through a digital loop filter 35 to a digital-to-analog converter (DAC) 37, which converts the phase error code into an analog voltage for adjusting the output frequency of the VCO 15.
Because oscillator circuits of the type used in the carrier tracking stage of FIG. 1 employ analog components (VCO 15), they suffer from a number of deficiencies. For example, their output frequencies will vary with environmental conditions, such as time (aging) and temperature, as well as with other less influential factors. In addition, component-to-component manufacturing tolerances of these parts are satisfactory only within a prescribed rangexe2x80x94usually specified in the hundreds of parts per million (ppm). Further, compared to other components in the radio, oscillators are relatively expensive and prone to mechanical failure.
Due to the inherent inaccuracies in oscillator components of a radio receiver prevent data from being perfectly demodulated and delivered to downstream baseband processing circuitry with precise replication, compensation circuitry must be incorporated into the radio""s timing recovery and data demodulation signal processing stages. These circuits traditionally utilize additional voltage controlled oscillator components, which are tuned to frequencies such that the inaccuracies of the crystal and voltage controlled oscillator components used in each of the transmitter and receiver portions of the radio can be effectively eliminated on a long term averaged basis. Unfortunately, employing a voltage controlled oscillator in the compensation circuit introduces yet another level of inaccuracy, and adds to the cost of the overall radio design.
In accordance with the present invention, the above described shortcomings of conventional analog voltage controlled oscillator-based radio systems are effectively obviated by a new and improved digital-based data demodulator architecture, that employs a cordic rotator-based digital phase locked loop for carrier frequency tracking, and thereby removes the voltage controlled oscillator and its associated problems from the phase locked loop. In a demodulator application, a received signal, such as a spread spectrum-modulated BPSK signal, is multiplied in respective in-phase (I) and quadrature phase (Q) channel mixers by relative phase quadrature reference frequency signals produced by a fixed frequency (e.g., crystal) oscillator and an associated 90xc2x0 phase shifter to produce down-converted (baseband) I and Q channels.
The I and Q channels are digitized and then despread by a correlator. The respective despread baseband I and Q channels are coupled to respective inputs of a digital cordic rotator, which executes iterative phase-rotational adjustments of its digitized in-phase and quadrature inputs, in accordance with a phase angle vector code generated by digital phase error detection logic circuitry to which the rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values over a prescribed number of processing cycles.
Pursuant to a preferred embodiment, the cordic rotator includes a quadrant adjustment section upstream of respective I and Q channel rotation iteration loops, and a phase angle quadrant adjustment section upstream of a phase angle iteration loop. Each iteration through the pipeline signal processing paths for the respective I channel and Q channel rotation iteration loops and a phase angle iteration loop comprises four quarter cycles. The quadrant adjustment section is used at initialization to perform a quadrant adjustment of the I and Q input values, based upon the sign of the angle of rotation xcex8 supplied from the digital loop filter. In association with initialization of the I and Q channels, a phase angle quadrant adjustment section performs an offset correction of the vector code value of the angle of rotation xcex8, in accordance with whether the phase angle code vector falls within a prescribed window.
During the first subportion (quarter cycle) of a respective iteration, quadrant-adjusted IP and QP values are latched into associated I and Q registers, an incremental angle control code associated with the arctan of an iteration-defined power of one-half is generated, and the current value of iterated phase angle value is latched in an updated phase angle or xcex2 register. During a second quarter cycle, the respective values of the I and Q vectors are divided by two, by associated right-shift logic circuits and the results are multiplied by the most significant bit of the phase angle code xcex2 to produce delta I and Q codes. Also a delta phase angle value based upon the incremental angle code is stored.
During the third quarter cycle, an updated phase angle value corresponding to the sum of the delta phase angle value and the updated phase angle xcex2 is generated and latched. Also the delta I and Q codes produced during the second quarter cycle are summed with the previous I and Q values to produce updated I and Q codes, respectively. In the fourth cycle, the updated I and Q codes are latched, thus completing one iteration.
This process is repeated for K iterations (with the exception of the initialization operations carried out by the quadrant adjustment section for the I and Q loops and the phase angle quadrant adjustment section for the phase angle loop). In the fourth quarter cycle of the Kth iteration, the adjusted values of the I and Q channel codes are latched into output registers to provide respective xe2x80x98cordic-rotatedxe2x80x99 I and Q channel output values.